1. Field of the Invention
The present invention relates to designing and manufacturing MuGFET ESD Protection Devices.
2. Description of the Related Art
The FinFET transistor is the most widely studied multi-gate architecture for technology-scaling below 45 nm due to its excellent control of Short Channel Effects (SCE) and its compatibility with standard CMOS processing. In Trémouilles et al, “Understanding the Optimization of Sub-45 nm MuGFET Devices for ESD Applications”, ESD 2007, pp 408-415, a variety of ESD device parameters (failure current It2, holding voltage Vh, on-resistance Ron, leakage current and area consumption) of a Grounded-Gate-NMOS FinFET device were investigated as a function of different layout and process parameters. Among the layout and process parameters, there are always some which are fixed by the manufacturing process and others which can be chosen by the ESD design engineer to try and find a desired ESD performance.
In view of the interdependency of the layout and process parameters, i.e. the fact that changing one parameter inevitably influences one or more other parameters, Trémouilles et al. have acknowledged that the design of ESD protection for FinFET technology and hence more in general for MuGFET technology is very complex.